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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 46

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Rev Log message Author Age Path
46 cosmetic updates unneback 5227d 01h /versatile_mem_ctrl/trunk/rtl/verilog/
45 added unneback 5227d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
44 registered row comparison unneback 5229d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
42 added pipeline stage for egress FIFO readot unneback 5229d 17h /versatile_mem_ctrl/trunk/rtl/verilog/
41 Added two alternate data capture functions. mikaeljf 5230d 01h /versatile_mem_ctrl/trunk/rtl/verilog/
40 updated fifo interfaces with re/rd and we/wr unneback 5230d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
39 updated FIFO and SDR 16 unneback 5230d 19h /versatile_mem_ctrl/trunk/rtl/verilog/
38 casex in rw state to save logic unneback 5233d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
37 unneback 5233d 17h /versatile_mem_ctrl/trunk/rtl/verilog/
36 unneback 5233d 18h /versatile_mem_ctrl/trunk/rtl/verilog/
35 work for limited test case unneback 5234d 01h /versatile_mem_ctrl/trunk/rtl/verilog/
34 added unneback 5234d 01h /versatile_mem_ctrl/trunk/rtl/verilog/
33 work for limited test case, no cke inhibit for fifo empty unneback 5234d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
32 Updated the testbench to match the new wishbone interface. mikaeljf 5237d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5239d 00h /versatile_mem_ctrl/trunk/rtl/verilog/
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5239d 00h /versatile_mem_ctrl/trunk/rtl/verilog/
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5243d 02h /versatile_mem_ctrl/trunk/rtl/verilog/
27 unneback 5246d 18h /versatile_mem_ctrl/trunk/rtl/verilog/
26 compiles OK, not simulated unneback 5248d 17h /versatile_mem_ctrl/trunk/rtl/verilog/
25 unneback 5248d 20h /versatile_mem_ctrl/trunk/rtl/verilog/

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