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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 61

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Rev Log message Author Age Path
61 Fixed blocking/nonblocking assign issue in sdr_16 fsm julius 5259d 16h /versatile_mem_ctrl/trunk/rtl/verilog/
60 Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation. julius 5259d 16h /versatile_mem_ctrl/trunk/rtl/verilog/
59 counter changed to shift register unneback 5259d 18h /versatile_mem_ctrl/trunk/rtl/verilog/
58 sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm julius 5260d 19h /versatile_mem_ctrl/trunk/rtl/verilog/
57 added support for early termination of burst access unneback 5261d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
56 corrected fifo_rd_data in state w4d unneback 5263d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
55 Fixed up sdr16 dqm output julius 5264d 08h /versatile_mem_ctrl/trunk/rtl/verilog/
54 dqm moved into FSM unneback 5265d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
53 unneback 5265d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
52 act exit for read updated unneback 5266d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
51 act exit for read updated unneback 5266d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5266d 10h /versatile_mem_ctrl/trunk/rtl/verilog/
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5266d 11h /versatile_mem_ctrl/trunk/rtl/verilog/
48 dq_oe fix unneback 5266d 11h /versatile_mem_ctrl/trunk/rtl/verilog/
47 support for registered outputs on ras, cas and we unneback 5266d 12h /versatile_mem_ctrl/trunk/rtl/verilog/
46 cosmetic updates unneback 5266d 13h /versatile_mem_ctrl/trunk/rtl/verilog/
45 added unneback 5266d 15h /versatile_mem_ctrl/trunk/rtl/verilog/
44 registered row comparison unneback 5268d 15h /versatile_mem_ctrl/trunk/rtl/verilog/
42 added pipeline stage for egress FIFO readot unneback 5269d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
41 Added two alternate data capture functions. mikaeljf 5269d 12h /versatile_mem_ctrl/trunk/rtl/verilog/

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