OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 63

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
63 Fixed a couple of sdr_16 bugs to do with tracking of opened banks julius 5241d 15h /versatile_mem_ctrl/trunk/rtl/verilog/
62 Added note to sdr_16_defines.v asking if it's still used julius 5241d 17h /versatile_mem_ctrl/trunk/rtl/verilog/
61 Fixed blocking/nonblocking assign issue in sdr_16 fsm julius 5245d 15h /versatile_mem_ctrl/trunk/rtl/verilog/
60 Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation. julius 5245d 15h /versatile_mem_ctrl/trunk/rtl/verilog/
59 counter changed to shift register unneback 5245d 17h /versatile_mem_ctrl/trunk/rtl/verilog/
58 sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm julius 5246d 18h /versatile_mem_ctrl/trunk/rtl/verilog/
57 added support for early termination of burst access unneback 5247d 20h /versatile_mem_ctrl/trunk/rtl/verilog/
56 corrected fifo_rd_data in state w4d unneback 5249d 13h /versatile_mem_ctrl/trunk/rtl/verilog/
55 Fixed up sdr16 dqm output julius 5250d 08h /versatile_mem_ctrl/trunk/rtl/verilog/
54 dqm moved into FSM unneback 5251d 05h /versatile_mem_ctrl/trunk/rtl/verilog/
53 unneback 5251d 05h /versatile_mem_ctrl/trunk/rtl/verilog/
52 act exit for read updated unneback 5252d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
51 act exit for read updated unneback 5252d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5252d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5252d 10h /versatile_mem_ctrl/trunk/rtl/verilog/
48 dq_oe fix unneback 5252d 11h /versatile_mem_ctrl/trunk/rtl/verilog/
47 support for registered outputs on ras, cas and we unneback 5252d 11h /versatile_mem_ctrl/trunk/rtl/verilog/
46 cosmetic updates unneback 5252d 12h /versatile_mem_ctrl/trunk/rtl/verilog/
45 added unneback 5252d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
44 registered row comparison unneback 5254d 14h /versatile_mem_ctrl/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.