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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 64

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Rev Log message Author Age Path
64 Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file julius 5171d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
63 Fixed a couple of sdr_16 bugs to do with tracking of opened banks julius 5171d 16h /versatile_mem_ctrl/trunk/rtl/verilog/
62 Added note to sdr_16_defines.v asking if it's still used julius 5171d 18h /versatile_mem_ctrl/trunk/rtl/verilog/
61 Fixed blocking/nonblocking assign issue in sdr_16 fsm julius 5175d 17h /versatile_mem_ctrl/trunk/rtl/verilog/
60 Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation. julius 5175d 17h /versatile_mem_ctrl/trunk/rtl/verilog/
59 counter changed to shift register unneback 5175d 18h /versatile_mem_ctrl/trunk/rtl/verilog/
58 sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm julius 5176d 19h /versatile_mem_ctrl/trunk/rtl/verilog/
57 added support for early termination of burst access unneback 5177d 22h /versatile_mem_ctrl/trunk/rtl/verilog/
56 corrected fifo_rd_data in state w4d unneback 5179d 15h /versatile_mem_ctrl/trunk/rtl/verilog/
55 Fixed up sdr16 dqm output julius 5180d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
54 dqm moved into FSM unneback 5181d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
53 unneback 5181d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
52 act exit for read updated unneback 5182d 08h /versatile_mem_ctrl/trunk/rtl/verilog/
51 act exit for read updated unneback 5182d 08h /versatile_mem_ctrl/trunk/rtl/verilog/
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5182d 11h /versatile_mem_ctrl/trunk/rtl/verilog/
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5182d 12h /versatile_mem_ctrl/trunk/rtl/verilog/
48 dq_oe fix unneback 5182d 12h /versatile_mem_ctrl/trunk/rtl/verilog/
47 support for registered outputs on ras, cas and we unneback 5182d 13h /versatile_mem_ctrl/trunk/rtl/verilog/
46 cosmetic updates unneback 5182d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
45 added unneback 5182d 16h /versatile_mem_ctrl/trunk/rtl/verilog/

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