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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 74

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Rev Log message Author Age Path
74 Minor update of rtl Makefile. mikaeljf 5190d 15h /versatile_mem_ctrl/trunk/rtl/verilog/
73 Minor updates to fix lost revisions 69 and 70. mikaeljf 5190d 16h /versatile_mem_ctrl/trunk/rtl/verilog/
72 Restored lost revisions 69 and 70. mikaeljf 5190d 17h /versatile_mem_ctrl/trunk/rtl/verilog/
71 Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes julius 5190d 18h /versatile_mem_ctrl/trunk/rtl/verilog/
70 mikaeljf 5194d 00h /versatile_mem_ctrl/trunk/rtl/verilog/
69 mikaeljf 5194d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
68 cleaqnup unneback 5196d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
67 added FSM for wb if unneback 5196d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
66 unneback 5196d 12h /versatile_mem_ctrl/trunk/rtl/verilog/
65 added unneback 5196d 12h /versatile_mem_ctrl/trunk/rtl/verilog/
64 Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file julius 5197d 11h /versatile_mem_ctrl/trunk/rtl/verilog/
63 Fixed a couple of sdr_16 bugs to do with tracking of opened banks julius 5197d 19h /versatile_mem_ctrl/trunk/rtl/verilog/
62 Added note to sdr_16_defines.v asking if it's still used julius 5197d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
61 Fixed blocking/nonblocking assign issue in sdr_16 fsm julius 5201d 19h /versatile_mem_ctrl/trunk/rtl/verilog/
60 Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation. julius 5201d 19h /versatile_mem_ctrl/trunk/rtl/verilog/
59 counter changed to shift register unneback 5201d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
58 sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm julius 5202d 22h /versatile_mem_ctrl/trunk/rtl/verilog/
57 added support for early termination of burst access unneback 5204d 00h /versatile_mem_ctrl/trunk/rtl/verilog/
56 corrected fifo_rd_data in state w4d unneback 5205d 17h /versatile_mem_ctrl/trunk/rtl/verilog/
55 Fixed up sdr16 dqm output julius 5206d 12h /versatile_mem_ctrl/trunk/rtl/verilog/

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