OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 78

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5187d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5195d 02h /versatile_mem_ctrl/trunk/rtl/verilog/
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5200d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
75 mikaeljf 5200d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
74 Minor update of rtl Makefile. mikaeljf 5204d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
73 Minor updates to fix lost revisions 69 and 70. mikaeljf 5204d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
72 Restored lost revisions 69 and 70. mikaeljf 5204d 05h /versatile_mem_ctrl/trunk/rtl/verilog/
71 Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes julius 5204d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
70 mikaeljf 5207d 12h /versatile_mem_ctrl/trunk/rtl/verilog/
69 mikaeljf 5208d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
68 cleaqnup unneback 5209d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
67 added FSM for wb if unneback 5209d 21h /versatile_mem_ctrl/trunk/rtl/verilog/
66 unneback 5210d 00h /versatile_mem_ctrl/trunk/rtl/verilog/
65 added unneback 5210d 00h /versatile_mem_ctrl/trunk/rtl/verilog/
64 Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file julius 5210d 23h /versatile_mem_ctrl/trunk/rtl/verilog/
63 Fixed a couple of sdr_16 bugs to do with tracking of opened banks julius 5211d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
62 Added note to sdr_16_defines.v asking if it's still used julius 5211d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
61 Fixed blocking/nonblocking assign issue in sdr_16 fsm julius 5215d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
60 Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation. julius 5215d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
59 counter changed to shift register unneback 5215d 09h /versatile_mem_ctrl/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.