OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 83

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
82 mikaeljf 5132d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
81 mikaeljf 5133d 05h /versatile_mem_ctrl/trunk/rtl/verilog/
80 mikaeljf 5133d 06h /versatile_mem_ctrl/trunk/rtl/verilog/
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5170d 20h /versatile_mem_ctrl/trunk/rtl/verilog/
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5173d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5181d 01h /versatile_mem_ctrl/trunk/rtl/verilog/
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5186d 02h /versatile_mem_ctrl/trunk/rtl/verilog/
75 mikaeljf 5186d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
74 Minor update of rtl Makefile. mikaeljf 5190d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
73 Minor updates to fix lost revisions 69 and 70. mikaeljf 5190d 03h /versatile_mem_ctrl/trunk/rtl/verilog/
72 Restored lost revisions 69 and 70. mikaeljf 5190d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
71 Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes julius 5190d 05h /versatile_mem_ctrl/trunk/rtl/verilog/
70 mikaeljf 5193d 11h /versatile_mem_ctrl/trunk/rtl/verilog/
69 mikaeljf 5194d 08h /versatile_mem_ctrl/trunk/rtl/verilog/
68 cleaqnup unneback 5195d 20h /versatile_mem_ctrl/trunk/rtl/verilog/
67 added FSM for wb if unneback 5195d 20h /versatile_mem_ctrl/trunk/rtl/verilog/
66 unneback 5195d 23h /versatile_mem_ctrl/trunk/rtl/verilog/
65 added unneback 5195d 23h /versatile_mem_ctrl/trunk/rtl/verilog/
64 Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file julius 5196d 23h /versatile_mem_ctrl/trunk/rtl/verilog/
63 Fixed a couple of sdr_16 bugs to do with tracking of opened banks julius 5197d 06h /versatile_mem_ctrl/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.