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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 85

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Rev Log message Author Age Path
85 Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo. mikaeljf 5102d 15h /versatile_mem_ctrl/trunk/rtl/verilog/
84 mikaeljf 5106d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
82 mikaeljf 5107d 14h /versatile_mem_ctrl/trunk/rtl/verilog/
81 mikaeljf 5108d 10h /versatile_mem_ctrl/trunk/rtl/verilog/
80 mikaeljf 5108d 11h /versatile_mem_ctrl/trunk/rtl/verilog/
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5146d 01h /versatile_mem_ctrl/trunk/rtl/verilog/
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5148d 08h /versatile_mem_ctrl/trunk/rtl/verilog/
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5156d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5161d 07h /versatile_mem_ctrl/trunk/rtl/verilog/
75 mikaeljf 5161d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
74 Minor update of rtl Makefile. mikaeljf 5165d 08h /versatile_mem_ctrl/trunk/rtl/verilog/
73 Minor updates to fix lost revisions 69 and 70. mikaeljf 5165d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
72 Restored lost revisions 69 and 70. mikaeljf 5165d 09h /versatile_mem_ctrl/trunk/rtl/verilog/
71 Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes julius 5165d 10h /versatile_mem_ctrl/trunk/rtl/verilog/
70 mikaeljf 5168d 16h /versatile_mem_ctrl/trunk/rtl/verilog/
69 mikaeljf 5169d 13h /versatile_mem_ctrl/trunk/rtl/verilog/
68 cleaqnup unneback 5171d 01h /versatile_mem_ctrl/trunk/rtl/verilog/
67 added FSM for wb if unneback 5171d 01h /versatile_mem_ctrl/trunk/rtl/verilog/
66 unneback 5171d 04h /versatile_mem_ctrl/trunk/rtl/verilog/
65 added unneback 5171d 04h /versatile_mem_ctrl/trunk/rtl/verilog/

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