URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [sim/] [rtl_sim/] - Rev 95

Rev	Log message	Author	Age	Path
86		mikaeljf	5101d 09h	/versatile_mem_ctrl/trunk/sim/rtl_sim/
82		mikaeljf	5107d 08h	/versatile_mem_ctrl/trunk/sim/rtl_sim/
80		mikaeljf	5108d 05h	/versatile_mem_ctrl/trunk/sim/rtl_sim/
75		mikaeljf	5161d 02h	/versatile_mem_ctrl/trunk/sim/rtl_sim/
70		mikaeljf	5168d 10h	/versatile_mem_ctrl/trunk/sim/rtl_sim/
69		mikaeljf	5169d 07h	/versatile_mem_ctrl/trunk/sim/rtl_sim/
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5195d 01h	/versatile_mem_ctrl/trunk/sim/rtl_sim/
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5199d 03h	/versatile_mem_ctrl/trunk/sim/rtl_sim/
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5227d 06h	/versatile_mem_ctrl/trunk/sim/rtl_sim/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5232d 02h	/versatile_mem_ctrl/trunk/sim/rtl_sim/