URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [sim/] [rtl_sim/] [bin/] - Rev 86

Rev	Log message	Author	Age	Path
86		mikaeljf	5128d 19h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin/
82		mikaeljf	5134d 17h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin/
80		mikaeljf	5135d 15h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin/
75		mikaeljf	5188d 12h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin/
70		mikaeljf	5195d 20h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin/
69		mikaeljf	5196d 16h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin/
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5222d 11h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin/
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5226d 13h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin/
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5254d 15h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5259d 12h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin/