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[/] [versatile_mem_ctrl/] [trunk/] [syn/] - Rev 28

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22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5224d 02h /versatile_mem_ctrl/trunk/syn/
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5228d 06h /versatile_mem_ctrl/trunk/syn/
20 Minor update of sdc-file. mikaeljf 5230d 07h /versatile_mem_ctrl/trunk/syn/
19 Added do-file for Modelsim waveform viewer. mikaeljf 5236d 12h /versatile_mem_ctrl/trunk/syn/
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5241d 08h /versatile_mem_ctrl/trunk/syn/
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5331d 13h /versatile_mem_ctrl/trunk/syn/

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