URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [syn/] - Rev 83

Rev	Log message	Author	Age	Path
83		mikaeljf	5268d 10h	/versatile_mem_ctrl/trunk/syn/
81		mikaeljf	5269d 11h	/versatile_mem_ctrl/trunk/syn/
75		mikaeljf	5322d 10h	/versatile_mem_ctrl/trunk/syn/
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5356d 08h	/versatile_mem_ctrl/trunk/syn/
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5376d 03h	/versatile_mem_ctrl/trunk/syn/
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5380d 07h	/versatile_mem_ctrl/trunk/syn/
20	Minor update of sdc-file.	mikaeljf	5382d 08h	/versatile_mem_ctrl/trunk/syn/
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5388d 13h	/versatile_mem_ctrl/trunk/syn/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5393d 09h	/versatile_mem_ctrl/trunk/syn/
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5483d 14h	/versatile_mem_ctrl/trunk/syn/