URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [syn/] [altera/] [bin/] - Rev 86

Rev	Log message	Author	Age	Path
86		mikaeljf	5116d 12h	/versatile_mem_ctrl/trunk/syn/altera/bin/
84		mikaeljf	5121d 11h	/versatile_mem_ctrl/trunk/syn/altera/bin/
83		mikaeljf	5122d 06h	/versatile_mem_ctrl/trunk/syn/altera/bin/
81		mikaeljf	5123d 07h	/versatile_mem_ctrl/trunk/syn/altera/bin/
75		mikaeljf	5176d 06h	/versatile_mem_ctrl/trunk/syn/altera/bin/
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5210d 04h	/versatile_mem_ctrl/trunk/syn/altera/bin/
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5229d 23h	/versatile_mem_ctrl/trunk/syn/altera/bin/
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5234d 03h	/versatile_mem_ctrl/trunk/syn/altera/bin/
20	Minor update of sdc-file.	mikaeljf	5236d 04h	/versatile_mem_ctrl/trunk/syn/altera/bin/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5247d 05h	/versatile_mem_ctrl/trunk/syn/altera/bin/