URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [tags/] [rel_1/] [bench/] [verilog/] - Rev 62

Rev	Log message	Author	Age	Path
62	New directory structure.	root	5562d 02h	/vga_lcd/tags/rel_1/bench/verilog/
42	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8078d 01h	/vga_lcd/tags/rel_1/bench/verilog/
38	Changed testbench to reflect modified VGA timing generator.	rherveille	8078d 02h	/vga_lcd/tags/rel_1/bench/verilog/
29	Added wb_ack delay section to testbench	rherveille	8150d 07h	/vga_lcd/tags/rel_1/bench/verilog/
26	Added 32bpp tests	rherveille	8160d 09h	/vga_lcd/tags/rel_1/bench/verilog/
24	Updated testbench for VGA/LCD Core version 2.0	rherveille	8234d 05h	/vga_lcd/tags/rel_1/bench/verilog/
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8320d 06h	/vga_lcd/tags/rel_1/bench/verilog/