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[/] [vga_lcd/] [tags/] [rel_1/] [rtl/] - Rev 62

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Rev Log message Author Age Path
62 New directory structure. root 5567d 20h /vga_lcd/tags/rel_1/rtl/
42 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8083d 19h /vga_lcd/tags/rel_1/rtl/
39 Changed video timing generator.
Changed wishbone master vertical gate count code.
Fixed a potential bug in the wishbone slave (cursor color register readout).		 rherveille 8083d 20h /vga_lcd/tags/rel_1/rtl/
37 Fixed a potential reset bug in the hint & vint generation. rherveille 8099d 00h /vga_lcd/tags/rel_1/rtl/
36 Fixed two small bugs that only showed up when the hardware cursors were disabled rherveille 8107d 01h /vga_lcd/tags/rel_1/rtl/
34 Added hardware cursor support to wishbone master.
Added provision to turn-off 3D cursors.
Fixed some minor bugs.		 rherveille 8130d 14h /vga_lcd/tags/rel_1/rtl/
33 Added 64x64pixels 4bpp hardware cursor support. rherveille 8130d 19h /vga_lcd/tags/rel_1/rtl/
32 Fixed dat_o incomplete sensitivity list. rherveille 8138d 00h /vga_lcd/tags/rel_1/rtl/
31 Some minor bug-fixes.
Changed vga_ssel into vga_curproc (cursor processor).		 rherveille 8146d 20h /vga_lcd/tags/rel_1/rtl/
30 Fixed some bugs discovered by modified testbench
Removed / Changed some strange logic constructions
Started work on hardware cursor support (not finished yet)
Changed top-level name to vga_enh_top.v		 rherveille 8156d 01h /vga_lcd/tags/rel_1/rtl/
28 Changed counter-library.
Changed vga-core.
Added 32bpp mode.		 rherveille 8166d 03h /vga_lcd/tags/rel_1/rtl/
23 Added Copyright/Licence header rherveille 8240d 19h /vga_lcd/tags/rel_1/rtl/
20 Switched parameter order. rherveille 8269d 20h /vga_lcd/tags/rel_1/rtl/
19 Major revisions throughout the core.
Moved Color Lookup Table inside core.
Changed control & status register contents.
Changed port names to be conform to new naming convention.
Fixed bug in CAB assertion.
Changed video memory address generation.
and many more ....		 rherveille 8269d 21h /vga_lcd/tags/rel_1/rtl/
18 Removed files. They are not used anymore. rherveille 8298d 18h /vga_lcd/tags/rel_1/rtl/
17 Major rework.
Included generic memory models.
Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)		 rherveille 8298d 18h /vga_lcd/tags/rel_1/rtl/
16 - Changed Directory Structure
- Added verilog Source Code
- Changed IO pin names and defines statements		 rudi 8326d 01h /vga_lcd/tags/rel_1/rtl/

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