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[/] [vga_lcd/] [tags/] [rel_1/] [rtl/] - Rev 28

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Rev Log message Author Age Path
28 Changed counter-library.
Changed vga-core.
Added 32bpp mode.
rherveille 8224d 02h /vga_lcd/tags/rel_1/rtl/
23 Added Copyright/Licence header rherveille 8298d 18h /vga_lcd/tags/rel_1/rtl/
20 Switched parameter order. rherveille 8327d 20h /vga_lcd/tags/rel_1/rtl/
19 Major revisions throughout the core.
Moved Color Lookup Table inside core.
Changed control & status register contents.
Changed port names to be conform to new naming convention.
Fixed bug in CAB assertion.
Changed video memory address generation.
and many more ....
rherveille 8327d 21h /vga_lcd/tags/rel_1/rtl/
18 Removed files. They are not used anymore. rherveille 8356d 18h /vga_lcd/tags/rel_1/rtl/
17 Major rework.
Included generic memory models.
Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)
rherveille 8356d 18h /vga_lcd/tags/rel_1/rtl/
16 - Changed Directory Structure
- Added verilog Source Code
- Changed IO pin names and defines statements
rudi 8384d 00h /vga_lcd/tags/rel_1/rtl/

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