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[/] [vga_lcd/] [tags/] [rel_19/] - Rev 16

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Rev Log message Author Age Path
16 - Changed Directory Structure
- Added verilog Source Code
- Changed IO pin names and defines statements		 rudi 8459d 18h /vga_lcd/tags/rel_19/
15 Created directory structure (documentation, vhdl, verilog) rherveille 8495d 08h /vga_lcd/tags/rel_19/
14 Added CLUT bank switching.
Replaced multiplier with simple counters.
Fixed timing bug.		 rherveille 8496d 03h /vga_lcd/tags/rel_19/
13 Replaced csm.vhd by csm_pb.vhd. Core does not require CLKx2 clock anymore. rherveille 8496d 15h /vga_lcd/tags/rel_19/
12 Added new top-level and sub-level (vga_and_clut.vhd & csm.vhd);
adds color-lookup-table to the VGA core (i.e. on-chip CLUT).
Ram generation has been tested with Altera and Xilinx parts.		 rherveille 8505d 19h /vga_lcd/tags/rel_19/
11 Major bug fixes in Wishbone Master and ColorProcessor blocks.
Core did not respond correctly to delayed ACK_I signals.

Added built-in Color Lookup Tables.		 rherveille 8505d 19h /vga_lcd/tags/rel_19/
10 Design now uses Xilinx-BlockRAMs instead of selectRAM rherveille 8512d 10h /vga_lcd/tags/rel_19/
9 no message rherveille 8513d 04h /vga_lcd/tags/rel_19/
8 Revised core. Removed unused signals rherveille 8518d 12h /vga_lcd/tags/rel_19/
7 revised counter.vhd rherveille 8522d 14h /vga_lcd/tags/rel_19/
6 no message rherveille 8523d 14h /vga_lcd/tags/rel_19/
5 Fixed a bug in wishbone master. Updated simulation files also rherveille 8527d 14h /vga_lcd/tags/rel_19/
4 changed wishbone address sections. rherveille 8538d 14h /vga_lcd/tags/rel_19/
2 initial release rherveille 8551d 18h /vga_lcd/tags/rel_19/
1 Standard project directories initialized by cvs2svn. 8551d 18h /vga_lcd/tags/rel_19/

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