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[/] [vga_lcd/] [tags/] [rel_19/] [bench/] [verilog/] - Rev 62

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Rev Log message Author Age Path
62 New directory structure. root 5585d 00h /vga_lcd/tags/rel_19/bench/verilog/
61 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7579d 21h /vga_lcd/tags/rel_19/bench/verilog/
60 all WB outputs are registered, but just when we dont use cursors markom 7579d 21h /vga_lcd/tags/rel_19/bench/verilog/
59 Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors. rherveille 7612d 03h /vga_lcd/tags/rel_19/bench/verilog/
58 Enabled Fifo Underrun test rherveille 7612d 03h /vga_lcd/tags/rel_19/bench/verilog/
54 Added DVI tests rherveille 7718d 20h /vga_lcd/tags/rel_19/bench/verilog/
52 Numerous updates and added checks rherveille 7719d 01h /vga_lcd/tags/rel_19/bench/verilog/
46 Added WISHBONE revB.3 sanity checks rherveille 7767d 17h /vga_lcd/tags/rel_19/bench/verilog/
44 Changed timing section in VGA core, changed testbench accordingly.
Fixed bug in 'timing check' test.		 rherveille 7767d 22h /vga_lcd/tags/rel_19/bench/verilog/
38 Changed testbench to reflect modified VGA timing generator. rherveille 8101d 01h /vga_lcd/tags/rel_19/bench/verilog/
29 Added wb_ack delay section to testbench rherveille 8173d 05h /vga_lcd/tags/rel_19/bench/verilog/
26 Added 32bpp tests rherveille 8183d 07h /vga_lcd/tags/rel_19/bench/verilog/
24 Updated testbench for VGA/LCD Core version 2.0 rherveille 8257d 03h /vga_lcd/tags/rel_19/bench/verilog/
16 - Changed Directory Structure
- Added verilog Source Code
- Changed IO pin names and defines statements		 rudi 8343d 05h /vga_lcd/tags/rel_19/bench/verilog/

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