URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk/] [bench/] [verilog/] - Rev 62

Rev	Log message	Author	Age	Path
62	New directory structure.	root	5586d 21h	/vga_lcd/trunk/bench/verilog/
60	all WB outputs are registered, but just when we dont use cursors	markom	7581d 18h	/vga_lcd/trunk/bench/verilog/
59	Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors.	rherveille	7614d 00h	/vga_lcd/trunk/bench/verilog/
58	Enabled Fifo Underrun test	rherveille	7614d 00h	/vga_lcd/trunk/bench/verilog/
54	Added DVI tests	rherveille	7720d 17h	/vga_lcd/trunk/bench/verilog/
52	Numerous updates and added checks	rherveille	7720d 22h	/vga_lcd/trunk/bench/verilog/
46	Added WISHBONE revB.3 sanity checks	rherveille	7769d 14h	/vga_lcd/trunk/bench/verilog/
44	Changed timing section in VGA core, changed testbench accordingly. Fixed bug in 'timing check' test.	rherveille	7769d 19h	/vga_lcd/trunk/bench/verilog/
38	Changed testbench to reflect modified VGA timing generator.	rherveille	8102d 21h	/vga_lcd/trunk/bench/verilog/
29	Added wb_ack delay section to testbench	rherveille	8175d 02h	/vga_lcd/trunk/bench/verilog/
26	Added 32bpp tests	rherveille	8185d 04h	/vga_lcd/trunk/bench/verilog/
24	Updated testbench for VGA/LCD Core version 2.0	rherveille	8259d 00h	/vga_lcd/trunk/bench/verilog/
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8345d 02h	/vga_lcd/trunk/bench/verilog/