URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk/] [bench/] [verilog/] - Rev 38

Rev	Log message	Author	Age	Path
38	Changed testbench to reflect modified VGA timing generator.	rherveille	8217d 20h	/vga_lcd/trunk/bench/verilog/
29	Added wb_ack delay section to testbench	rherveille	8290d 00h	/vga_lcd/trunk/bench/verilog/
26	Added 32bpp tests	rherveille	8300d 02h	/vga_lcd/trunk/bench/verilog/
24	Updated testbench for VGA/LCD Core version 2.0	rherveille	8373d 23h	/vga_lcd/trunk/bench/verilog/
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8460d 00h	/vga_lcd/trunk/bench/verilog/