URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk/] [bench/] [verilog/] - Rev 44

Rev	Log message	Author	Age	Path
44	Changed timing section in VGA core, changed testbench accordingly. Fixed bug in 'timing check' test.	rherveille	7880d 03h	/vga_lcd/trunk/bench/verilog/
38	Changed testbench to reflect modified VGA timing generator.	rherveille	8213d 06h	/vga_lcd/trunk/bench/verilog/
29	Added wb_ack delay section to testbench	rherveille	8285d 10h	/vga_lcd/trunk/bench/verilog/
26	Added 32bpp tests	rherveille	8295d 12h	/vga_lcd/trunk/bench/verilog/
24	Updated testbench for VGA/LCD Core version 2.0	rherveille	8369d 09h	/vga_lcd/trunk/bench/verilog/
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8455d 10h	/vga_lcd/trunk/bench/verilog/