URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk/] [bench/] [verilog/] - Rev 52

Rev	Log message	Author	Age	Path
52	Numerous updates and added checks	rherveille	7725d 03h	/vga_lcd/trunk/bench/verilog/
46	Added WISHBONE revB.3 sanity checks	rherveille	7773d 19h	/vga_lcd/trunk/bench/verilog/
44	Changed timing section in VGA core, changed testbench accordingly. Fixed bug in 'timing check' test.	rherveille	7774d 00h	/vga_lcd/trunk/bench/verilog/
38	Changed testbench to reflect modified VGA timing generator.	rherveille	8107d 02h	/vga_lcd/trunk/bench/verilog/
29	Added wb_ack delay section to testbench	rherveille	8179d 07h	/vga_lcd/trunk/bench/verilog/
26	Added 32bpp tests	rherveille	8189d 09h	/vga_lcd/trunk/bench/verilog/
24	Updated testbench for VGA/LCD Core version 2.0	rherveille	8263d 05h	/vga_lcd/trunk/bench/verilog/
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8349d 07h	/vga_lcd/trunk/bench/verilog/