URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk/] [bench/] [verilog/] - Rev 59

Rev	Log message	Author	Age	Path
59	Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors.	rherveille	7665d 01h	/vga_lcd/trunk/bench/verilog/
58	Enabled Fifo Underrun test	rherveille	7665d 01h	/vga_lcd/trunk/bench/verilog/
54	Added DVI tests	rherveille	7771d 18h	/vga_lcd/trunk/bench/verilog/
52	Numerous updates and added checks	rherveille	7771d 23h	/vga_lcd/trunk/bench/verilog/
46	Added WISHBONE revB.3 sanity checks	rherveille	7820d 15h	/vga_lcd/trunk/bench/verilog/
44	Changed timing section in VGA core, changed testbench accordingly. Fixed bug in 'timing check' test.	rherveille	7820d 20h	/vga_lcd/trunk/bench/verilog/
38	Changed testbench to reflect modified VGA timing generator.	rherveille	8153d 23h	/vga_lcd/trunk/bench/verilog/
29	Added wb_ack delay section to testbench	rherveille	8226d 03h	/vga_lcd/trunk/bench/verilog/
26	Added 32bpp tests	rherveille	8236d 05h	/vga_lcd/trunk/bench/verilog/
24	Updated testbench for VGA/LCD Core version 2.0	rherveille	8310d 01h	/vga_lcd/trunk/bench/verilog/
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8396d 03h	/vga_lcd/trunk/bench/verilog/