URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] - Rev 19

Rev	Log message	Author	Age	Path
19	Major revisions throughout the core. Moved Color Lookup Table inside core. Changed control & status register contents. Changed port names to be conform to new naming convention. Fixed bug in CAB assertion. Changed video memory address generation. and many more ....	rherveille	8399d 00h	/vga_lcd/trunk/rtl/verilog/
18	Removed files. They are not used anymore.	rherveille	8427d 21h	/vga_lcd/trunk/rtl/verilog/
17	Major rework. Included generic memory models. Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)	rherveille	8427d 21h	/vga_lcd/trunk/rtl/verilog/
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8455d 03h	/vga_lcd/trunk/rtl/verilog/