URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] - Rev 31

Rev	Log message	Author	Age	Path
31	Some minor bug-fixes. Changed vga_ssel into vga_curproc (cursor processor).	rherveille	8311d 01h	/vga_lcd/trunk/rtl/verilog/
30	Fixed some bugs discovered by modified testbench Removed / Changed some strange logic constructions Started work on hardware cursor support (not finished yet) Changed top-level name to vga_enh_top.v	rherveille	8320d 06h	/vga_lcd/trunk/rtl/verilog/
28	Changed counter-library. Changed vga-core. Added 32bpp mode.	rherveille	8330d 08h	/vga_lcd/trunk/rtl/verilog/
23	Added Copyright/Licence header	rherveille	8405d 00h	/vga_lcd/trunk/rtl/verilog/
20	Switched parameter order.	rherveille	8434d 01h	/vga_lcd/trunk/rtl/verilog/
19	Major revisions throughout the core. Moved Color Lookup Table inside core. Changed control & status register contents. Changed port names to be conform to new naming convention. Fixed bug in CAB assertion. Changed video memory address generation. and many more ....	rherveille	8434d 02h	/vga_lcd/trunk/rtl/verilog/
18	Removed files. They are not used anymore.	rherveille	8463d 00h	/vga_lcd/trunk/rtl/verilog/
17	Major rework. Included generic memory models. Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)	rherveille	8463d 00h	/vga_lcd/trunk/rtl/verilog/
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8490d 06h	/vga_lcd/trunk/rtl/verilog/