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[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] - Rev 37

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Rev Log message Author Age Path
37 Fixed a potential reset bug in the hint & vint generation. rherveille 8159d 18h /vga_lcd/trunk/rtl/verilog/
36 Fixed two small bugs that only showed up when the hardware cursors were disabled rherveille 8167d 20h /vga_lcd/trunk/rtl/verilog/
34 Added hardware cursor support to wishbone master.
Added provision to turn-off 3D cursors.
Fixed some minor bugs.		 rherveille 8191d 09h /vga_lcd/trunk/rtl/verilog/
33 Added 64x64pixels 4bpp hardware cursor support. rherveille 8191d 14h /vga_lcd/trunk/rtl/verilog/
32 Fixed dat_o incomplete sensitivity list. rherveille 8198d 18h /vga_lcd/trunk/rtl/verilog/
31 Some minor bug-fixes.
Changed vga_ssel into vga_curproc (cursor processor).		 rherveille 8207d 14h /vga_lcd/trunk/rtl/verilog/
30 Fixed some bugs discovered by modified testbench
Removed / Changed some strange logic constructions
Started work on hardware cursor support (not finished yet)
Changed top-level name to vga_enh_top.v		 rherveille 8216d 19h /vga_lcd/trunk/rtl/verilog/
28 Changed counter-library.
Changed vga-core.
Added 32bpp mode.		 rherveille 8226d 21h /vga_lcd/trunk/rtl/verilog/
23 Added Copyright/Licence header rherveille 8301d 13h /vga_lcd/trunk/rtl/verilog/
20 Switched parameter order. rherveille 8330d 14h /vga_lcd/trunk/rtl/verilog/
19 Major revisions throughout the core.
Moved Color Lookup Table inside core.
Changed control & status register contents.
Changed port names to be conform to new naming convention.
Fixed bug in CAB assertion.
Changed video memory address generation.
and many more ....		 rherveille 8330d 16h /vga_lcd/trunk/rtl/verilog/
18 Removed files. They are not used anymore. rherveille 8359d 13h /vga_lcd/trunk/rtl/verilog/
17 Major rework.
Included generic memory models.
Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)		 rherveille 8359d 13h /vga_lcd/trunk/rtl/verilog/
16 - Changed Directory Structure
- Added verilog Source Code
- Changed IO pin names and defines statements		 rudi 8386d 19h /vga_lcd/trunk/rtl/verilog/

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