URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

[/] [virtex7_pcie_dma/] - Rev 6

Rev	Log message	Author	Age	Path
6	Changed: * fixed bug #1 First read of registers sometimes fails. Added extra pipeline stage on read / write enable * Fixed missing signals in sensitivity list	fransschreuder	3581d 15h	/virtex7_pcie_dma/
5	Changed: * Added two registers to test interrupts vectors 2 and 3 * Added a register to read generic constants to show number of interrupts / number of descriptors * fixed consistency of generic default values among different design units * fixed route of pll_locked / register map record, to allow non-flattening of synthesis	fransschreuder	3582d 19h	/virtex7_pcie_dma/
4	fixed a typo in the interrupt table documentation	fransschreuder	3594d 15h	/virtex7_pcie_dma/
3	Created: First commit of the full PCIe DMA Core Including: -Firmware -Vivado .tcl scripts -Questasim simulation scripts -Documentation (Latex / Doxygen script)	fransschreuder	3594d 16h	/virtex7_pcie_dma/
2	Added firmware directory	fransschreuder	3597d 14h	/virtex7_pcie_dma/
1	The project and the structure was created	root	3616d 09h	/virtex7_pcie_dma/