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URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

[/] [virtex7_pcie_dma/] [trunk/] - Rev 34

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Rev Log message Author Age Path
34 FIXED:
* Wrong TLP length reported on register writes
* Two simultaneous interrupts were not handled
* XADC wizard for ultrascale devices

Added:
* Added voltage (int, aux, bram) readout on XADC wizards
fransschreuder 2914d 14h /virtex7_pcie_dma/trunk/
33 ADDED:
-- supportedtools.tex, again to test the OC repo
aborga 2959d 13h /virtex7_pcie_dma/trunk/
32 MODIFIED:
-- minor things just to test OC svn repo
aborga 2959d 13h /virtex7_pcie_dma/trunk/
31 Added example application documentation. oussamak 3053d 15h /virtex7_pcie_dma/trunk/
30 Added:
* Wupper GUI with speed test and chain test
* Added wupper-dma-transfer, wupper-chaintest and wupper-write
* Several bug fixes in the Wupper tools
oussamak 3053d 15h /virtex7_pcie_dma/trunk/
29 Improved application to reflect both up and down transfers fransschreuder 3095d 13h /virtex7_pcie_dma/trunk/
28 Added registermap reset fransschreuder 3095d 15h /virtex7_pcie_dma/trunk/
27 Fixed:
* BUG 2580: Missing packets in receive (PC => FPGA) path

Changed:
* Client tags now handled by Xilinx IP core
* fifo signals to reflect upfifo and downfifo naming
fransschreuder 3095d 18h /virtex7_pcie_dma/trunk/
26 Added sys_clk constraint fransschreuder 3095d 20h /virtex7_pcie_dma/trunk/
25 Added scripts and constraints for KCU105 fransschreuder 3095d 20h /virtex7_pcie_dma/trunk/
24 Added:
* Support for KCU105 board in code
TODO
* Add constraints and build scripts for KCU105
fransschreuder 3096d 14h /virtex7_pcie_dma/trunk/
23 Fixed reset of application registers fransschreuder 3153d 19h /virtex7_pcie_dma/trunk/
22 Added dma_soft_reset to trigger register resets fransschreuder 3159d 19h /virtex7_pcie_dma/trunk/
21 Fixed BUG http://opencores.org/bug,view,2562 fransschreuder 3168d 16h /virtex7_pcie_dma/trunk/
20 Fixed:
* Missing packets if the fifo goes empty during a TLP
* Dynamically change the empty threshold of the main fifo to TLP size
fransschreuder 3182d 15h /virtex7_pcie_dma/trunk/
19 * driver/README updated oussamak 3188d 17h /virtex7_pcie_dma/trunk/
18 Changed:
* Added drivers
* Added Wupper tools for debugging
* Added card ID register
oussamak 3188d 19h /virtex7_pcie_dma/trunk/
17 Changed name of toplevel, to make tree consistent oussamak 3202d 21h /virtex7_pcie_dma/trunk/
16 MODIFED:
-- top level name to wupper_oc (including scripts)
aborga 3252d 15h /virtex7_pcie_dma/trunk/
15 MODIFIED:
-- Renamed core to Wupper (vhdl files)
-- Changed width of interrupt enable to number_of_interrupts
fransschreuder 3252d 15h /virtex7_pcie_dma/trunk/

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