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[/] [w11/] [tags/] [w11a_V0.7/] [rtl/] [vlib/] [simlib/] - Rev 33

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Rev Log message Author Age Path
33 - major release w11a_V0.70 (tagged) wfjm 3294d 20h /w11/tags/w11a_V0.7/rtl/vlib/simlib/
29 - added support for Vivado
- added support for Nexys4 and Basys3 boards
- added RL11 disk support
- lots of documentation updated		 wfjm 3398d 17h /w11/tags/w11a_V0.7/rtl/vlib/simlib/
27 - migrate to rlink protocol version 4
- Goals for rlink v4
- 16 bit addresses (instead of 8 bit)
- more robust encoding, support for error recovery at transport level
- add features to reduce round trips
- improved attention handling
- new 'list abort' command
- For further details see README_Rlink_V4.txt
- use own C++ based tcl shell tclshcpp instead of tclsh		 wfjm 3477d 19h /w11/tags/w11a_V0.7/rtl/vlib/simlib/
25 - The div instruction gave wrong results in some corner cases when either
divisor or quotient were the largest negative integer (100000 or -32768).
This is corrected now, for details see ECO-026-div.txt
- some minor updates and fixes to support scripts
- xtwi usage and XTWI_PATH setup explained in INSTALL.txt		 wfjm 3609d 22h /w11/tags/w11a_V0.7/rtl/vlib/simlib/
17 - interim release w11a_V0.56 (untagged)
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !!		 wfjm 4194d 15h /w11/tags/w11a_V0.7/rtl/vlib/simlib/
13 - interim release w11a_V0.532 (untagged)
- re-organize modules 'human I/O' interface on Digilent boards
- add test designs for 'human I/O' interface for atlys,nexys2, and s3board
- small updates in crc8 and dcm areas
- with one exception all vhdl sources use now numeric_std		 wfjm 4604d 00h /w11/tags/w11a_V0.7/rtl/vlib/simlib/
9 - interim release w11a_V0.52 (untagged)
- migrate to rbus protocol verion 3
- reorganize rbus and rlink modules, many renames		 wfjm 4925d 22h /w11/tags/w11a_V0.7/rtl/vlib/simlib/
8 - interim release w11a_V0.51 (untagged)
- migrate to ibus protocol verion 2
- nexys2 systems now with DCM derived system clock supported
- sys_w11a_n2 now runs with 58 MHz clksys		 wfjm 4961d 13h /w11/tags/w11a_V0.7/rtl/vlib/simlib/
3 setup all svn:ignore props wfjm 5102d 18h /w11/tags/w11a_V0.7/rtl/vlib/simlib/
2 initial source upload (no docs yet) wfjm 5102d 18h /w11/tags/w11a_V0.7/rtl/vlib/simlib/

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