URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

Subversion Repositories wb2axip

[/] [wb2axip/] [trunk/] [rtl/] - Rev 15

Rev	Log message	Author	Age	Path
15	Quick update, making this module verilatable again	dgisselq	2286d 14h	/wb2axip/trunk/rtl/
14	Added a reset line upon user request	dgisselq	2286d 15h	/wb2axip/trunk/rtl/
13	Bug fix release--fixes the bugs Antti pointed out.	dgisselq	2299d 04h	/wb2axip/trunk/rtl/
12	Added Verilators obj_dir to the list of ignored files	dgisselq	2396d 15h	/wb2axip/trunk/rtl/
8	The WB to AXI translator wrks and works well. A proof of this will be added shortly.	dgisselq	2396d 16h	/wb2axip/trunk/rtl/
7	Simplified.	dgisselq	2713d 16h	/wb2axip/trunk/rtl/
6	IT WORKS!!! (On non-pipelined data--havent tested it on pipelined stuff .. yet)	dgisselq	2841d 11h	/wb2axip/trunk/rtl/
5	Adjusted variable names to match the spec and the MIG.	dgisselq	2846d 02h	/wb2axip/trunk/rtl/
4	Adjusted the core quickly so it should work for 128-bit wide wishbone busses as well as 32-bit wide busses.	dgisselq	2846d 08h	/wb2axip/trunk/rtl/
3	Fixed the Verilator compile-time bugs. Still haven't tested the core.	dgisselq	2846d 08h	/wb2axip/trunk/rtl/
2	Initial check in. Core not (yet) tested, verified, or validated.	dgisselq	2846d 09h	/wb2axip/trunk/rtl/