URL https://opencores.org/ocsvn/wb_dma/wb_dma/trunk

Subversion Repositories wb_dma

[/] [wb_dma/] [trunk/] [rtl/] [verilog/] - Rev 17

Rev	Log message	Author	Age	Path
17	New directory structure.	root	5586d 20h	/wb_dma/trunk/rtl/verilog/
15	- Minor cleanup	rudi	8181d 05h	/wb_dma/trunk/rtl/verilog/
13	- Fixed problem where synthesis tools would instantiate latches instead of flip-flops	rudi	8275d 05h	/wb_dma/trunk/rtl/verilog/
10	- Made the core parameterized	rudi	8286d 02h	/wb_dma/trunk/rtl/verilog/
9	Changed reset to active high.	rudi	8327d 15h	/wb_dma/trunk/rtl/verilog/
8	- Changed IO names to be more clear. - Uniquifyed define names to be core specific. - Added Section 3.10, describing DMA restart.	rudi	8351d 01h	/wb_dma/trunk/rtl/verilog/
6	Split up priority encoder modules to separate files	rudi	8358d 23h	/wb_dma/trunk/rtl/verilog/
5	1) Changed Directory Structure 2) Added restart signal (REST)	rudi	8367d 22h	/wb_dma/trunk/rtl/verilog/