OpenCores
URL https://opencores.org/ocsvn/wb_dma/wb_dma/trunk

Subversion Repositories wb_dma

[/] [wb_dma/] [trunk/] [rtl/] [verilog/] - Rev 17

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
17 New directory structure. root 5577d 15h /wb_dma/trunk/rtl/verilog/
15 - Minor cleanup rudi 8171d 23h /wb_dma/trunk/rtl/verilog/
13 - Fixed problem where synthesis tools would instantiate latches instead of flip-flops rudi 8265d 23h /wb_dma/trunk/rtl/verilog/
10 - Made the core parameterized rudi 8276d 21h /wb_dma/trunk/rtl/verilog/
9 Changed reset to active high. rudi 8318d 10h /wb_dma/trunk/rtl/verilog/
8 - Changed IO names to be more clear.
- Uniquifyed define names to be core specific.
- Added Section 3.10, describing DMA restart.
rudi 8341d 20h /wb_dma/trunk/rtl/verilog/
6 Split up priority encoder modules to separate files rudi 8349d 17h /wb_dma/trunk/rtl/verilog/
5 1) Changed Directory Structure
2) Added restart signal (REST)
rudi 8358d 16h /wb_dma/trunk/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.