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[/] [wbddr3/] - Rev 5

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5 Under Verilator/simulation testing, the core now properly brings the device
up from reset. Next step: opening/closing banks.
dgisselq 3019d 14h /wbddr3/
4 Work continues. A preliminary test-bench has been created. The core
has yet to pass through the reset cycle yet, so there's a lot of work
still to be done.
dgisselq 3020d 06h /wbddr3/
3 Fixes some, not all, of the Verilator build/lint errors. dgisselq 3020d 22h /wbddr3/
2 Initial checkin. Pieces are not working yet, but the general approach is
starting to take shape.
dgisselq 3020d 23h /wbddr3/
1 The project and the structure was created root 3021d 03h /wbddr3/

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