URL https://opencores.org/ocsvn/wbuart32/wbuart32/trunk

Subversion Repositories wbuart32

[/] [wbuart32/] [trunk/] [bench/] [verilog/] - Rev 26

Rev	Log message	Author	Age	Path
26	Formally verified the TXUART core (plus others)	dgisselq	1918d 10h	/wbuart32/trunk/bench/verilog/
18	Lots of updates. See the git log for details	dgisselq	2406d 14h	/wbuart32/trunk/bench/verilog/
15	Added a set of lite-UARTs that only handle 8N1 to the repository.	dgisselq	2638d 21h	/wbuart32/trunk/bench/verilog/
13	Adjusted documentation of OPT_STANDALONE, and updated internal README files.	dgisselq	2674d 19h	/wbuart32/trunk/bench/verilog/
10	Adjusted for the new hardware flow control capability.	dgisselq	2674d 19h	/wbuart32/trunk/bench/verilog/
6	Lots of changes--see the git log for the full details.	dgisselq	2709d 01h	/wbuart32/trunk/bench/verilog/
5	Created independent peripheral, several toplevel tests, and updated documentation to match.	dgisselq	2719d 11h	/wbuart32/trunk/bench/verilog/
2	A first version to be checked in. The rxuart.v and txuart.v files have been well tested elsewhere, although the test setup here has not been as well tested. Still, type 'make test' in the base directory and you will get an assurance that the entire thing works--if you would like.	dgisselq	2852d 20h	/wbuart32/trunk/bench/verilog/