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Rev Log message Author Age Path
18 Complete XGCHN test code rehayes 5393d 07h /xgate/
17 Additions for XGCHID debug commands rehayes 5393d 07h /xgate/
16 Copy of what was in the bench directory rehayes 5393d 07h /xgate/
15 Fix R1 load at boot up, add debug features rehayes 5406d 05h /xgate/
14 Sept 23 2009 Change update rehayes 5407d 07h /xgate/
13 Debug functions test code rehayes 5407d 07h /xgate/
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5407d 07h /xgate/
11 Update with Single Step debuging test rehayes 5407d 07h /xgate/
10 Minor Cleanup rehayes 5412d 07h /xgate/
9 Update for new testbench usage rehayes 5413d 05h /xgate/
8 Clean up, Fix default ISR rehayes 5413d 05h /xgate/
7 Fix to take advantage of change to sconv program. rehayes 5419d 04h /xgate/
6 Update to create output file name from input file name by changing extension to .v rehayes 5419d 05h /xgate/
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5420d 07h /xgate/
4 Clean up rehayes 5428d 05h /xgate/
3 Clean up rehayes 5428d 05h /xgate/
2 Initial Checkin rehayes 5428d 05h /xgate/
1 The project was created and the structure was created root 5460d 10h /xgate/

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