URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] - Rev 19

Rev	Log message	Author	Age	Path
19	Verilog memory image for testing	rehayes	5426d 22h	/xgate/
18	Complete XGCHN test code	rehayes	5426d 22h	/xgate/
17	Additions for XGCHID debug commands	rehayes	5426d 22h	/xgate/
16	Copy of what was in the bench directory	rehayes	5426d 22h	/xgate/
15	Fix R1 load at boot up, add debug features	rehayes	5439d 20h	/xgate/
14	Sept 23 2009 Change update	rehayes	5440d 22h	/xgate/
13	Debug functions test code	rehayes	5440d 22h	/xgate/
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5440d 22h	/xgate/
11	Update with Single Step debuging test	rehayes	5440d 22h	/xgate/
10	Minor Cleanup	rehayes	5445d 22h	/xgate/
9	Update for new testbench usage	rehayes	5446d 21h	/xgate/
8	Clean up, Fix default ISR	rehayes	5446d 21h	/xgate/
7	Fix to take advantage of change to sconv program.	rehayes	5452d 20h	/xgate/
6	Update to create output file name from input file name by changing extension to .v	rehayes	5452d 20h	/xgate/
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5453d 22h	/xgate/
4	Clean up	rehayes	5461d 20h	/xgate/
3	Clean up	rehayes	5461d 20h	/xgate/
2	Initial Checkin	rehayes	5461d 20h	/xgate/
1	The project was created and the structure was created	root	5494d 01h	/xgate/