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Rev Log message Author Age Path
58 WISHBONE Bus update. rehayes 5263d 11h /xgate/
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5263d 14h /xgate/
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5279d 15h /xgate/
55 Minor change to instruction set details. rehayes 5279d 15h /xgate/
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5279d 15h /xgate/
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5279d 15h /xgate/
52 Minor changes to aide waveform debug rehayes 5279d 15h /xgate/
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5295d 11h /xgate/
50 incremental update to match status bit changes rehayes 5295d 11h /xgate/
49 First pass with instruction set details rehayes 5295d 12h /xgate/
48 Update for SBC ana ADC condition code changes rehayes 5295d 12h /xgate/
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5295d 12h /xgate/
46 Update to remove stack registers and add new register text. rehayes 5327d 10h /xgate/
45 Update to remove stack registers and add new register text. rehayes 5327d 10h /xgate/
44 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5329d 09h /xgate/
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5329d 09h /xgate/
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5329d 09h /xgate/
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5330d 11h /xgate/
40 Update for single program counter adder rehayes 5350d 14h /xgate/
39 delete rehayes 5358d 15h /xgate/

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