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[/] [xgate/] - Rev 67

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Rev Log message Author Age Path
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5160d 07h /xgate/
66 Fix testbench and RISC core related to debug mode and wait states. rehayes 5180d 03h /xgate/
65 Parameterize delays based on number of RAM wait states. rehayes 5180d 03h /xgate/
64 Fixed more bugs related to wait states and debug mode. rehayes 5180d 03h /xgate/
63 Remove historical output ports that are no longer used. rehayes 5190d 03h /xgate/
62 Cleanup implicit wire declarations. rehayes 5190d 03h /xgate/
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5197d 02h /xgate/
60 Add ability at insert wait states on RAM access rehayes 5197d 02h /xgate/
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5197d 02h /xgate/
58 WISHBONE Bus update. rehayes 5249d 02h /xgate/
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5249d 05h /xgate/
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5265d 06h /xgate/
55 Minor change to instruction set details. rehayes 5265d 06h /xgate/
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5265d 06h /xgate/
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5265d 06h /xgate/
52 Minor changes to aide waveform debug rehayes 5265d 06h /xgate/
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5281d 02h /xgate/
50 incremental update to match status bit changes rehayes 5281d 02h /xgate/
49 First pass with instruction set details rehayes 5281d 03h /xgate/
48 Update for SBC ana ADC condition code changes rehayes 5281d 03h /xgate/

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