OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] - Rev 76

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
76 Updated xgate_risc.v for xlink synthesis warnings. rehayes 5149d 13h /xgate/
75 Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 rehayes 5149d 14h /xgate/
74 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5154d 15h /xgate/
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5154d 15h /xgate/
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5154d 15h /xgate/
71 Added irq bypass registers to rtl, testbench and doc. rehayes 5155d 17h /xgate/
70 Updated with interrupt bypass controll registers. rehayes 5155d 17h /xgate/
69 New test to verify irq interrupt priority encoder. rehayes 5155d 18h /xgate/
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5155d 18h /xgate/
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5155d 18h /xgate/
66 Fix testbench and RISC core related to debug mode and wait states. rehayes 5175d 14h /xgate/
65 Parameterize delays based on number of RAM wait states. rehayes 5175d 14h /xgate/
64 Fixed more bugs related to wait states and debug mode. rehayes 5175d 14h /xgate/
63 Remove historical output ports that are no longer used. rehayes 5185d 13h /xgate/
62 Cleanup implicit wire declarations. rehayes 5185d 13h /xgate/
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5192d 13h /xgate/
60 Add ability at insert wait states on RAM access rehayes 5192d 13h /xgate/
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5192d 13h /xgate/
58 WISHBONE Bus update. rehayes 5244d 13h /xgate/
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5244d 16h /xgate/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.