URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] - Rev 20

Rev	Log message	Author	Age	Path
20	Added event signal for compare error tracking in top level test bench.	rehayes	5393d 02h	/xgate/trunk/
19	Verilog memory image for testing	rehayes	5393d 02h	/xgate/trunk/
18	Complete XGCHN test code	rehayes	5393d 02h	/xgate/trunk/
17	Additions for XGCHID debug commands	rehayes	5393d 02h	/xgate/trunk/
16	Copy of what was in the bench directory	rehayes	5393d 02h	/xgate/trunk/
15	Fix R1 load at boot up, add debug features	rehayes	5406d 00h	/xgate/trunk/
14	Sept 23 2009 Change update	rehayes	5407d 02h	/xgate/trunk/
13	Debug functions test code	rehayes	5407d 02h	/xgate/trunk/
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5407d 02h	/xgate/trunk/
11	Update with Single Step debuging test	rehayes	5407d 02h	/xgate/trunk/
10	Minor Cleanup	rehayes	5412d 02h	/xgate/trunk/
9	Update for new testbench usage	rehayes	5413d 00h	/xgate/trunk/
8	Clean up, Fix default ISR	rehayes	5413d 01h	/xgate/trunk/
7	Fix to take advantage of change to sconv program.	rehayes	5418d 23h	/xgate/trunk/
6	Update to create output file name from input file name by changing extension to .v	rehayes	5419d 00h	/xgate/trunk/
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5420d 02h	/xgate/trunk/
4	Clean up	rehayes	5428d 00h	/xgate/trunk/
3	Clean up	rehayes	5428d 00h	/xgate/trunk/
2	Initial Checkin	rehayes	5428d 00h	/xgate/trunk/
1	The project was created and the structure was created	root	5460d 05h	/xgate/trunk/