OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] - Rev 67

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5297d 09h /xgate/trunk/
66 Fix testbench and RISC core related to debug mode and wait states. rehayes 5317d 05h /xgate/trunk/
65 Parameterize delays based on number of RAM wait states. rehayes 5317d 05h /xgate/trunk/
64 Fixed more bugs related to wait states and debug mode. rehayes 5317d 05h /xgate/trunk/
63 Remove historical output ports that are no longer used. rehayes 5327d 05h /xgate/trunk/
62 Cleanup implicit wire declarations. rehayes 5327d 05h /xgate/trunk/
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5334d 04h /xgate/trunk/
60 Add ability at insert wait states on RAM access rehayes 5334d 04h /xgate/trunk/
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5334d 04h /xgate/trunk/
58 WISHBONE Bus update. rehayes 5386d 04h /xgate/trunk/
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5386d 07h /xgate/trunk/
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5402d 08h /xgate/trunk/
55 Minor change to instruction set details. rehayes 5402d 08h /xgate/trunk/
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5402d 08h /xgate/trunk/
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5402d 08h /xgate/trunk/
52 Minor changes to aide waveform debug rehayes 5402d 08h /xgate/trunk/
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5418d 04h /xgate/trunk/
50 incremental update to match status bit changes rehayes 5418d 04h /xgate/trunk/
49 First pass with instruction set details rehayes 5418d 05h /xgate/trunk/
48 Update for SBC ana ADC condition code changes rehayes 5418d 05h /xgate/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.