OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [bench/] - Rev 67

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
65 Parameterize delays based on number of RAM wait states. rehayes 5292d 11h /xgate/trunk/bench/
62 Cleanup implicit wire declarations. rehayes 5302d 11h /xgate/trunk/bench/
60 Add ability at insert wait states on RAM access rehayes 5309d 11h /xgate/trunk/bench/
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5377d 14h /xgate/trunk/bench/
50 incremental update to match status bit changes rehayes 5393d 11h /xgate/trunk/bench/
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5428d 10h /xgate/trunk/bench/
39 delete rehayes 5456d 14h /xgate/trunk/bench/
37 RAM model breakout for testbench rehayes 5456d 15h /xgate/trunk/bench/
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5456d 15h /xgate/trunk/bench/
35 Add byte lane select input to all tasks rehayes 5456d 15h /xgate/trunk/bench/
27 Subversion test, no actual code changes rehayes 5481d 09h /xgate/trunk/bench/
21 Added timeout, total error count, and XGCHN test rehayes 5489d 10h /xgate/trunk/bench/
20 Added event signal for compare error tracking in top level test bench. rehayes 5489d 10h /xgate/trunk/bench/
19 Verilog memory image for testing rehayes 5489d 10h /xgate/trunk/bench/
18 Complete XGCHN test code rehayes 5489d 10h /xgate/trunk/bench/
13 Debug functions test code rehayes 5503d 11h /xgate/trunk/bench/
11 Update with Single Step debuging test rehayes 5503d 11h /xgate/trunk/bench/
10 Minor Cleanup rehayes 5508d 11h /xgate/trunk/bench/
9 Update for new testbench usage rehayes 5509d 09h /xgate/trunk/bench/
8 Clean up, Fix default ISR rehayes 5509d 09h /xgate/trunk/bench/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.