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[/] [xgate/] [trunk/] [bench/] - Rev 77

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Rev Log message Author Age Path
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5159d 06h /xgate/trunk/bench/
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5160d 09h /xgate/trunk/bench/
65 Parameterize delays based on number of RAM wait states. rehayes 5180d 05h /xgate/trunk/bench/
62 Cleanup implicit wire declarations. rehayes 5190d 04h /xgate/trunk/bench/
60 Add ability at insert wait states on RAM access rehayes 5197d 04h /xgate/trunk/bench/
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5265d 08h /xgate/trunk/bench/
50 incremental update to match status bit changes rehayes 5281d 04h /xgate/trunk/bench/
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5316d 04h /xgate/trunk/bench/
39 delete rehayes 5344d 08h /xgate/trunk/bench/
37 RAM model breakout for testbench rehayes 5344d 09h /xgate/trunk/bench/
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5344d 09h /xgate/trunk/bench/
35 Add byte lane select input to all tasks rehayes 5344d 09h /xgate/trunk/bench/
27 Subversion test, no actual code changes rehayes 5369d 02h /xgate/trunk/bench/
21 Added timeout, total error count, and XGCHN test rehayes 5377d 04h /xgate/trunk/bench/
20 Added event signal for compare error tracking in top level test bench. rehayes 5377d 04h /xgate/trunk/bench/
19 Verilog memory image for testing rehayes 5377d 04h /xgate/trunk/bench/
18 Complete XGCHN test code rehayes 5377d 04h /xgate/trunk/bench/
13 Debug functions test code rehayes 5391d 04h /xgate/trunk/bench/
11 Update with Single Step debuging test rehayes 5391d 04h /xgate/trunk/bench/
10 Minor Cleanup rehayes 5396d 04h /xgate/trunk/bench/

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