URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [bench/] [verilog/] - Rev 54

Rev	Log message	Author	Age	Path
54	complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module.	rehayes	5278d 22h	/xgate/trunk/bench/verilog/
50	incremental update to match status bit changes	rehayes	5294d 19h	/xgate/trunk/bench/verilog/
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5329d 19h	/xgate/trunk/bench/verilog/
37	RAM model breakout for testbench	rehayes	5358d 00h	/xgate/trunk/bench/verilog/
36	Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls.	rehayes	5358d 00h	/xgate/trunk/bench/verilog/
35	Add byte lane select input to all tasks	rehayes	5358d 00h	/xgate/trunk/bench/verilog/
27	Subversion test, no actual code changes	rehayes	5382d 17h	/xgate/trunk/bench/verilog/
21	Added timeout, total error count, and XGCHN test	rehayes	5390d 19h	/xgate/trunk/bench/verilog/
20	Added event signal for compare error tracking in top level test bench.	rehayes	5390d 19h	/xgate/trunk/bench/verilog/
19	Verilog memory image for testing	rehayes	5390d 19h	/xgate/trunk/bench/verilog/
11	Update with Single Step debuging test	rehayes	5404d 19h	/xgate/trunk/bench/verilog/
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5417d 19h	/xgate/trunk/bench/verilog/
2	Initial Checkin	rehayes	5425d 17h	/xgate/trunk/bench/verilog/