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[/] [xgate/] [trunk/] [bench/] [verilog/] - Rev 62

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Rev Log message Author Age Path
62 Cleanup implicit wire declarations. rehayes 5191d 21h /xgate/trunk/bench/verilog/
60 Add ability at insert wait states on RAM access rehayes 5198d 20h /xgate/trunk/bench/verilog/
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5267d 00h /xgate/trunk/bench/verilog/
50 incremental update to match status bit changes rehayes 5282d 20h /xgate/trunk/bench/verilog/
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5317d 20h /xgate/trunk/bench/verilog/
37 RAM model breakout for testbench rehayes 5346d 01h /xgate/trunk/bench/verilog/
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5346d 01h /xgate/trunk/bench/verilog/
35 Add byte lane select input to all tasks rehayes 5346d 01h /xgate/trunk/bench/verilog/
27 Subversion test, no actual code changes rehayes 5370d 19h /xgate/trunk/bench/verilog/
21 Added timeout, total error count, and XGCHN test rehayes 5378d 20h /xgate/trunk/bench/verilog/
20 Added event signal for compare error tracking in top level test bench. rehayes 5378d 20h /xgate/trunk/bench/verilog/
19 Verilog memory image for testing rehayes 5378d 20h /xgate/trunk/bench/verilog/
11 Update with Single Step debuging test rehayes 5392d 21h /xgate/trunk/bench/verilog/
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5405d 21h /xgate/trunk/bench/verilog/
2 Initial Checkin rehayes 5413d 18h /xgate/trunk/bench/verilog/

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