OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [bench/] [verilog/] - Rev 93

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
93 Initial revision, memory image for skipjack test. rehayes 4611d 19h /xgate/trunk/bench/verilog/
89 Code cleanup. rehayes 4625d 18h /xgate/trunk/bench/verilog/
86 Add JTAG test tasks rehayes 4825d 17h /xgate/trunk/bench/verilog/
82 Added debug module to assist in software debugging. rehayes 5100d 21h /xgate/trunk/bench/verilog/
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5191d 01h /xgate/trunk/bench/verilog/
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5192d 04h /xgate/trunk/bench/verilog/
65 Parameterize delays based on number of RAM wait states. rehayes 5212d 00h /xgate/trunk/bench/verilog/
62 Cleanup implicit wire declarations. rehayes 5222d 00h /xgate/trunk/bench/verilog/
60 Add ability at insert wait states on RAM access rehayes 5228d 23h /xgate/trunk/bench/verilog/
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5297d 03h /xgate/trunk/bench/verilog/
50 incremental update to match status bit changes rehayes 5312d 23h /xgate/trunk/bench/verilog/
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5347d 23h /xgate/trunk/bench/verilog/
37 RAM model breakout for testbench rehayes 5376d 04h /xgate/trunk/bench/verilog/
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5376d 04h /xgate/trunk/bench/verilog/
35 Add byte lane select input to all tasks rehayes 5376d 04h /xgate/trunk/bench/verilog/
27 Subversion test, no actual code changes rehayes 5400d 22h /xgate/trunk/bench/verilog/
21 Added timeout, total error count, and XGCHN test rehayes 5408d 23h /xgate/trunk/bench/verilog/
20 Added event signal for compare error tracking in top level test bench. rehayes 5408d 23h /xgate/trunk/bench/verilog/
19 Verilog memory image for testing rehayes 5408d 23h /xgate/trunk/bench/verilog/
11 Update with Single Step debuging test rehayes 5423d 00h /xgate/trunk/bench/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.