URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [doc/] [src/] - Rev 96

Rev	Log message	Author	Age	Path
85	Corrections to instruction set details example code, added test bench debugger.	rehayes	5146d 15h	/xgate/trunk/doc/src/
80	Added IRQ bypass registers and Test bench appendix	rehayes	5209d 10h	/xgate/trunk/doc/src/
79	Added IRQ bypass registers and Test bench appendix	rehayes	5209d 10h	/xgate/trunk/doc/src/
70	Updated with interrupt bypass controll registers.	rehayes	5238d 15h	/xgate/trunk/doc/src/
55	Minor change to instruction set details.	rehayes	5343d 15h	/xgate/trunk/doc/src/
49	First pass with instruction set details	rehayes	5359d 12h	/xgate/trunk/doc/src/
45	Update to remove stack registers and add new register text.	rehayes	5391d 10h	/xgate/trunk/doc/src/
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5394d 11h	/xgate/trunk/doc/src/
33	Update with some new pin information	rehayes	5422d 16h	/xgate/trunk/doc/src/
22	Updated with figures and some new features	rehayes	5455d 11h	/xgate/trunk/doc/src/
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5482d 12h	/xgate/trunk/doc/src/
2	Initial Checkin	rehayes	5490d 09h	/xgate/trunk/doc/src/