OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] - Rev 61

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5244d 18h /xgate/trunk/rtl/
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5296d 21h /xgate/trunk/rtl/
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5312d 22h /xgate/trunk/rtl/
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5328d 19h /xgate/trunk/rtl/
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5362d 16h /xgate/trunk/rtl/
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5362d 16h /xgate/trunk/rtl/
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5363d 18h /xgate/trunk/rtl/
40 Update for single program counter adder rehayes 5383d 21h /xgate/trunk/rtl/
34 minor changes related to wishbone master interface rehayes 5391d 23h /xgate/trunk/rtl/
31 Cleanup for MAX_CHANNEL bus rehayes 5403d 18h /xgate/trunk/rtl/
30 Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus rehayes 5403d 18h /xgate/trunk/rtl/
29 Added some constant assigments, still needs more work to complete rehayes 5403d 18h /xgate/trunk/rtl/
28 Added comment line rehayes 5403d 18h /xgate/trunk/rtl/
26 Add synopsys commands, add else defaults for semphore state machine. rehayes 5418d 20h /xgate/trunk/rtl/
25 Fix connected net name rehayes 5418d 20h /xgate/trunk/rtl/
24 Delete unused inputs rehayes 5418d 21h /xgate/trunk/rtl/
17 Additions for XGCHID debug commands rehayes 5424d 18h /xgate/trunk/rtl/
15 Fix R1 load at boot up, add debug features rehayes 5437d 16h /xgate/trunk/rtl/
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5438d 19h /xgate/trunk/rtl/
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5451d 19h /xgate/trunk/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.