URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] - Rev 41

Rev	Log message	Author	Age	Path
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5347d 21h	/xgate/trunk/rtl/verilog/
40	Update for single program counter adder	rehayes	5368d 00h	/xgate/trunk/rtl/verilog/
34	minor changes related to wishbone master interface	rehayes	5376d 02h	/xgate/trunk/rtl/verilog/
31	Cleanup for MAX_CHANNEL bus	rehayes	5387d 21h	/xgate/trunk/rtl/verilog/
30	Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus	rehayes	5387d 21h	/xgate/trunk/rtl/verilog/
29	Added some constant assigments, still needs more work to complete	rehayes	5387d 21h	/xgate/trunk/rtl/verilog/
28	Added comment line	rehayes	5387d 22h	/xgate/trunk/rtl/verilog/
26	Add synopsys commands, add else defaults for semphore state machine.	rehayes	5402d 23h	/xgate/trunk/rtl/verilog/
25	Fix connected net name	rehayes	5402d 23h	/xgate/trunk/rtl/verilog/
24	Delete unused inputs	rehayes	5403d 00h	/xgate/trunk/rtl/verilog/
17	Additions for XGCHID debug commands	rehayes	5408d 21h	/xgate/trunk/rtl/verilog/
15	Fix R1 load at boot up, add debug features	rehayes	5421d 19h	/xgate/trunk/rtl/verilog/
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5422d 22h	/xgate/trunk/rtl/verilog/
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5435d 22h	/xgate/trunk/rtl/verilog/
2	Initial Checkin	rehayes	5443d 20h	/xgate/trunk/rtl/verilog/