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[/] [xgate/] [trunk/] [rtl/] [verilog/] - Rev 42

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Rev Log message Author Age Path
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5353d 17h /xgate/trunk/rtl/verilog/
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5354d 19h /xgate/trunk/rtl/verilog/
40 Update for single program counter adder rehayes 5374d 21h /xgate/trunk/rtl/verilog/
34 minor changes related to wishbone master interface rehayes 5382d 23h /xgate/trunk/rtl/verilog/
31 Cleanup for MAX_CHANNEL bus rehayes 5394d 18h /xgate/trunk/rtl/verilog/
30 Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus rehayes 5394d 19h /xgate/trunk/rtl/verilog/
29 Added some constant assigments, still needs more work to complete rehayes 5394d 19h /xgate/trunk/rtl/verilog/
28 Added comment line rehayes 5394d 19h /xgate/trunk/rtl/verilog/
26 Add synopsys commands, add else defaults for semphore state machine. rehayes 5409d 20h /xgate/trunk/rtl/verilog/
25 Fix connected net name rehayes 5409d 20h /xgate/trunk/rtl/verilog/
24 Delete unused inputs rehayes 5409d 21h /xgate/trunk/rtl/verilog/
17 Additions for XGCHID debug commands rehayes 5415d 19h /xgate/trunk/rtl/verilog/
15 Fix R1 load at boot up, add debug features rehayes 5428d 17h /xgate/trunk/rtl/verilog/
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5429d 19h /xgate/trunk/rtl/verilog/
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5442d 19h /xgate/trunk/rtl/verilog/
2 Initial Checkin rehayes 5450d 17h /xgate/trunk/rtl/verilog/

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