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[/] [xgate/] [trunk/] [rtl/] [verilog/] - Rev 89

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Rev	Log message	Author	Age	Path
89	Code cleanup.	rehayes	4593d 17h	/xgate/trunk/rtl/verilog/
88	Updated with complete code	rehayes	4667d 02h	/xgate/trunk/rtl/verilog/
87	First pass JTAG TAP, state machine working but needs work to complete reset of TAP.	rehayes	4793d 17h	/xgate/trunk/rtl/verilog/
75	Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382	rehayes	5153d 23h	/xgate/trunk/rtl/verilog/
72	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5159d 00h	/xgate/trunk/rtl/verilog/
67	Added irq bypass function and controll registers. Made lowest interrupt index highest priority.	rehayes	5160d 03h	/xgate/trunk/rtl/verilog/
64	Fixed more bugs related to wait states and debug mode.	rehayes	5179d 23h	/xgate/trunk/rtl/verilog/
63	Remove historical output ports that are no longer used.	rehayes	5189d 23h	/xgate/trunk/rtl/verilog/
59	Fix bug in entering DEBUG mode from WB bus command	rehayes	5196d 23h	/xgate/trunk/rtl/verilog/
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5249d 01h	/xgate/trunk/rtl/verilog/
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5265d 02h	/xgate/trunk/rtl/verilog/
47	Fix status bit error in ADC and SBC instruction, fix error in thread startup.	rehayes	5280d 23h	/xgate/trunk/rtl/verilog/
43	Update for single program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5314d 20h	/xgate/trunk/rtl/verilog/
42	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5314d 21h	/xgate/trunk/rtl/verilog/
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5315d 23h	/xgate/trunk/rtl/verilog/
40	Update for single program counter adder	rehayes	5336d 01h	/xgate/trunk/rtl/verilog/
34	minor changes related to wishbone master interface	rehayes	5344d 03h	/xgate/trunk/rtl/verilog/
31	Cleanup for MAX_CHANNEL bus	rehayes	5355d 22h	/xgate/trunk/rtl/verilog/
30	Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus	rehayes	5355d 23h	/xgate/trunk/rtl/verilog/
29	Added some constant assigments, still needs more work to complete	rehayes	5355d 23h	/xgate/trunk/rtl/verilog/

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[/] [xgate/] [trunk/] [rtl/] [verilog/] - Rev 89

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